Nowadays designs of an integrated circuit tend to be more complex, coupled with size inflation and increasingly advanced techniques. Hierarchical design is a most common design method for an integrated circuit chip, wherein the chip to be designed will be divided into a plurality of sub modules, each sub module being separately designed and then called by a top level. If, in the design, several sub modules are completely identical, the design of a whole chip is completed with only designing the sub module once and by calling the designed sub module multiple times when designing the top level. Such a sub module is called a reused sub module which can greatly reduce the complexity and work load of design.
However, when a reused sub module is called multiple times by a top level design, the timing variation between respective reused sub modules is always different, which makes the designer have to make repetitive adjustments. To cope with timing variation of a reused sub module, the following methods are usually adopted in the prior art, starting from reducing the timing variation inside the module:                Logical method: in order to reduce timing variation on a data path, typically, a device with a greater drive capability is used so as to reduce logic fan-out and a device with a higher threshold voltage is replaced with one with a lower threshold voltage; and in design, adopted approaches are typically copying/relaying logics, re-synthesis and optimization, etc.        Physical method: in order to make data paths as short as possible, locations of some modules will be adjusted to make them as close as possible, and in design, it is embodied as adjustment of pre-arranged locations; or the number of power capacitors may be increased or decreased so as to reduce the noise of power supply, which is embodied as adjustment of power supply capacity, etc.        
However, the above methods not only are time-consuming but also can hardly solve timing variations between reused sub modules. For a complex design, this part of work will account for 10% to 20% of the final stage working time.